As a request for high-density packaging of the semiconductor circuit chips of a large scale integration (abbreviated to “LSI”) has risen, it has been proposed to enhance a packaging density by stacking the semiconductor circuit chips in a vertical direction, namely, in the thickness direction of a circuit board.
There is a semiconductor apparatus wherein, in order to realize the high-density packaging, the semiconductor circuit chips stacked by tape carrier packages are respectively connected to a circuit board. In such a semiconductor apparatus, tape carriers include identification signal lines so as to be capable of identifying the individual chips. Hereinafter, the semiconductor circuit chips will be simply stated as “chips” in some cases.
FIG. 11 is a perspective view showing a semiconductor apparatus in which chips 2 are stacked using tape carriers 1, and the semiconductor apparatus in which the three chips 2 are stacked is shown in FIG. 11. Each of the chips 2 includes a first chip side terminal 3 to which a chip selection signal for selecting the operation of the individual chip 2 is input, and second terminals 4 to and from which other signals are input and output. Besides, a circuit board includes terminals 5a-5b on a first circuit board side for providing the chip selection signals to the respective chips 2 independently of one another, and terminals 6 on a second circuit board side for providing and accepting the other signals.
The tape carriers 1 include wiring lines 7 which connect the first and second chip side terminals 3, 4 and the first and second circuit board side terminals 5, 6, respectively. The tape carriers 1 are disposed separately from the chips 2, and are formed by being stacked similarly to the chips 1. In FIG. 11, the tape carriers 1 are parts indicated by oblique lines.
In such a semiconductor apparatus, the pattern of those parts 8 of the wiring lines 7 which are to be connected with the first circuit board side terminals 5 is redundantly created beforehand, and in mounting tape carrier packages, each of which consists of the tape carrier 1 and the chip 2, on the circuit board, the necessary wiring line parts are left behind, and the unnecessary wiring line parts are cut away. Thus, as shown in FIG. 11, the chip selection signals can be fed to the respective chips 2 independently of one another, and the stacked chips 2 are made identifiable using the chip selection signals.
As the operating speed and functions of the chips 2 have been heightened, there occurs the problem that, with the packages employing the tape carriers 1 as stated above, the performances of the chips 2 cannot be satisfactorily demonstrated on account of signal delays ascribable to the wiring lines.
In view of such a problem, it has been proposed in the first prior art that chips having electrodes each of which penetrates vertically through the corresponding chip are stacked into a module (refer to, for example, the specification of U.S. Pat. No. 6,141,245). For the chips to be stacked, the individual chips need to be identified as in the contrivance in the case of realizing the multilayered module of the tape carrier packages.
FIGS. 12-14 are views for explaining a semiconductor apparatus which is configured by stacking chips that have electrodes penetrating vertically through the chips. For the sake of description, only the penetrating leads depicted with hatched lines which penetrate through the chips, and wiring lines which extend between these penetrating leads depicted with hatched lines and the connection terminals 14-16 of the chips, are illustrated in FIGS. 12-14, and the chips, inter-layer insulating films, etc. are not illustrated. Besides, only the wiring lines relevant to chip selection signals are shown in FIGS. 12-14. Also, the case of stacking the three chips as in the semiconductor apparatus shown in FIG. 11 will be described here. The penetrating electrodes depicted with hatched lines penetrate through the chips in the stacked direction of these chips.
FIG. 12 is a perspective view showing a chip selection wiring line 17 which is a wiring line laid in the chip of lower stage when the chips have been stacked, and which transmits the chip selection signal for selecting the operation of this chip. FIG. 13 is a perspective view showing a chip selection wiring line 18 which is laid in the chip of middle stage. FIG. 14 is a perspective view showing a chip selection wiring line 19 laid in the chip of upper stage.
The lower-stage chip includes the chip side connection terminal 14 to which the chip selection signal is input, the penetrating electrodes 21, 22, 23 which penetrate through this chip and which serve to connect the chip side connection terminal 14 and any terminal disposed on a circuit board, a connection line 24 which serves to connect the chip side connection terminal 14 and the penetrating electrode 21 with each other, and connection terminals 25, 26 which connect the penetrating electrodes 22, 23 and the terminals of the stacked middle-stage chip. The penetrating electrodes 22, 23 are leads for transmitting the chip selection signals to the stacked middle-stage and upper-stage chips. In FIG. 12, the penetrating electrodes 21, 22, 23 are indicated by oblique lines, and the connection line 24 is indicated by meshed lines.
The middle-stage chip includes the chip side connection terminal 15 to which the chip selection signal is input, penetrating electrodes 27, 28 which penetrate through this chip and which are respectively connected with the penetrating electrodes 22, 23 disposed in the lower-stage chip, through the connection terminals 25, 26, a connection line 29 which serves to connect the chip side connection terminal 15 and the penetrating electrode 27 with each other, and a connection terminal 31 which connects the penetrating electrode 28 and the terminal of the stacked upper-stage chip. The penetrating electrode 28 is a lead for transmitting the chip selection signal to the stacked upper-stage chip. Unlike the lower-stage chip, the middle-stage chip suffices with a configuration in which only the two penetrating electrodes are disposed. That is, even when a penetrating electrode 32 indicated by phantom lines in FIG. 13 is made, it is not connected. In FIG. 13, the penetrating electrodes 27, 28 are indicated by oblique lines, and the connection line 29 is indicated by meshed lines.
The upper-stage chip includes the chip side connection terminal 16 to which the chip selection signal is input, a penetrating electrode 33 which penetrates through this chip and which is connected with the penetrating electrode 28 disposed in the lower-stage chip, through the connection terminal 31, and a connection line 34 which serves to connect the chip side connection terminal 16 and the penetrating electrode 33 with each other. Unlike the lower-stage and middle-stage chips, the upper-stage chip suffices with a configuration in which only one penetrating electrode is disposed. That is, even when penetrating electrodes 35, 36 indicated by phantom lines in FIG. 14 are made, they are not connected. In FIG. 14, the penetrating electrode 33 is indicated by oblique lines, and the connection line 34 is indicated by meshed lines.
The wiring patterns shown in FIGS. 12-14 need to be provided in the chips beforehand. That is, the chip to be stacked is fabricated as a chip separated from the underlying chip, in a wafer process for fabricating the particular chip.
In a case where different sorts of chips are to be stacked, the mere stacking of them poses no problem because they are chips originally separated from one another. However, in a case where the same chips are to be stacked in a large number, for example, where a large-capacity memory is to be realized by stacking memories in a large number, the same chips cannot be stacked, so that the different sorts of chips need to be fabricated in the number of chips to-be-stacked, and a surplus labor is required.
Besides, in a semiconductor apparatus for realizing high-density packaging, there are mounted circuits for electrically testing whether or not the packaged chips are connected, that is, boundary scan controllers.
The boundary scan controller includes five signal lines; TDI (Test Data input: data input part), TDO (Test Data Output: data output part), TCK (Test Clock input: clock input part), TMS (Test Mode Select input: test mode input part) and TRST (Test Reset input: test reset input part) on account of the standards of a boundary scan test. Herein, the signal line TRST is optional.
In a boundary scan which conforms to the standards of the JTAG (Joint European Test Action Group), the signal lines TDI and TDO of the boundary scan controllers incorporated in the individual chips in the semiconductor apparatus are connected in the shape of a chain. Hereinafter, the chain-like connection of the boundary scan controllers will be sometimes stated as “daisy chain”. The signal lines TCK, TMS, TDI and TRST shall be generally termed “input section”.
Next, the technique of the boundary scan test will be described.
FIG. 15 is a circuit diagram showing the connection states of a plurality of chip assemblies IC which include boundary scan controllers, while FIG. 16 is a diagram showing a multilayered module 50 which is configured by stacking the chip assemblies IC in the circuit diagram of FIG. 15. The multilayered module 50 is configured in such a way that the plurality of chip assemblies IC1, IC2, . . . , ICn (where n denotes an integer of at least 3) are stacked. Hereinafter, the chip assemblies IC1-ICn shall be stated as “chips IC” when generally termed. A connector 52 is connected to the multilayered module 50, and a JTAG tester is connected to the connector 52. In FIG. 16, the chip assemblies IC shown are stacked at the lowermost stage, middle stage and uppermost stage in succession from the left.
The signal lines TCK, TMS or TRST in the respective chip assemblies IC are connected to the corresponding pin of the connector 52 in parallel with one another through wiring patterns provided in these chip assemblies IC. On the other hand, regarding the signal lines TDI and TDO, the signal lines TDO of the chip assemblies IC on the preceding stage side are successively connected in cascade to the signal lines TDI of the chip assemblies IC on the succeeding stage side. Besides, the signal line TDI of the chip assembly IC1 of the first stage and the signal line TDO of the chip assembly ICn of the uppermost stage are connected to the respectively corresponding pins of the connector 52.
In the multilayered module 50 thus configured, the chip assemblies IC are controlled by the JTAG tester, whereby the boundary scan test is performed simultaneously for all the chip assemblies IC.
In the multilayered module 50, only the chip assembly ICn to be stacked at the uppermost stage needs to have connections different from those of the chip assemblies except this chip assembly ICn. Therefore, only the chip assembly ICn at the uppermost stage needs to be fabricated separately from the other chips by a wafer process.
FIGS. 17 and 18 are perspective views showing the wiring patterns of the chip assemblies in the multilayered module 50 shown in FIG. 16, and the case of stacking the chip assemblies by face-up is supposed in FIGS. 17 and 18. The “face-up” is a mounting method in which the chips are stacked with their circuit surfaces facing opposite to a circuit board. For the sake of description, only the penetrating electrodes depicted with hatched lines which are disposed in the chip assemblies, and wiring lines which extend between these penetrating electrodes depicted with hatched lines and the connection terminals 63 to 68 of the chips, are illustrated in FIGS. 17 and 18, and the chips, inter-layer insulating films, etc. are not illustrated.
FIG. 17 is the perspective view showing the wiring pattern of the chip assembly at each of the lowermost stage and the middle stage. The chip assembly at each of the lowermost stage and the middle stage includes the chip side connection terminal 63 of the TDI, the chip side connection terminal 64 of the TDO, the chip side connection terminal 65 for the bus connections of the TCK etc., the penetrating electrode 71 for transmitting the TDI signal, the connection line 72 for connecting the penetrating electrode 71 and the chip side connection terminal 63 of the TDI, a connection terminal 73 for transmitting a TDO signal to the chip of the upper stage, a connection line 74 on the chip for joining the chip side connection terminal 64 of the TDO and the connection terminal 73, the penetrating electrode 75 for the bus connections of the TCK etc., the connection line 76 on the chip for connecting the penetrating electrode 75 and the chip side connection terminal 65 for the bus connections of the TCK etc., a connection terminal 77 for transmitting the signals of the TCK etc. to the chip of the upper stage, and the penetrating electrode 78 for returning a TDO signal from the chip of the uppermost stage, to the lower stage.
FIG. 18 is the perspective view showing the wiring pattern of the chip assembly at the uppermost stage. The chip assembly of the uppermost stage includes the chip side connection terminal 63 of the TDI, the chip side connection terminal 64 of the TDO, the chip side connection terminal 65 for the bus connections of the TCK etc., the penetrating electrode 71 for transmitting a TDI signal, the connection line 72 for connecting the penetrating electrode 71 and the chip side connection terminal 63 of the TDI, the penetrating electrode 75 for the bus connections of the TCK etc., the connection line 76 on the chip for connecting the penetrating electrode 75 and the chip side connection terminal 65 for the bus connections of the TCK etc., the penetrating electrode 78 for returning the TDO signal from the chip of the uppermost stage, to the lower stage, and the connection line 79 for connecting the chip side connection terminal 64 of the TDO and the penetrating electrode 78.
The wiring pattern in the chip assembly at each of the lowermost stage and the middle stage and the wiring pattern in the chip assembly at the uppermost stage as respectively shown in FIGS. 17 and 18 need to be provided in the corresponding chip assemblies beforehand. That is, the chip assemblies to be stacked are fabricated as the separate chip assemblies in wafer processes. In the case of performing the boundary scans, it is only the chip assembly of the uppermost stage that needs to be made the separate chip assembly, as elucidated in FIGS. 17 and 18, but in a case where the same chips are to be stacked in a large number, for example, where a large-capacity memory is to be realized by stacking memories in a large number, there is the problem that the same chips cannot be stacked.